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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-05 14:37:31 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-05 14:37:31 +0200
commit5392b3d94038963a7121f391ad1b5075a5e32b8e (patch)
treec9f53d71a2837c78d919cceb76cbc922782c2088 /src/ram.v
parent1751c689d2005345b420d43584d7668c0ca93f6c (diff)
downloadriscv_cpu-5392b3d94038963a7121f391ad1b5075a5e32b8e.tar.gz
riscv_cpu-5392b3d94038963a7121f391ad1b5075a5e32b8e.zip
added memory unit
Diffstat (limited to 'src/ram.v')
-rw-r--r--src/ram.v31
1 files changed, 31 insertions, 0 deletions
diff --git a/src/ram.v b/src/ram.v
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+module ram #(
+ parameter N = 32,
+ parameter SIZE = 1024
+)(
+ input clk,
+ input rst,
+ input we,
+ input [log2(SIZE)-1:0] addr,
+ input [N-1:0] data_write,
+ output reg [N-1:0] data_read
+);
+
+`include "include/log2.vh"
+
+reg [8:0] ram_block [SIZE-1:0];
+
+integer i;
+always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ for (i = 0; i < SIZE; i = i + 1)
+ ram_block[i] <= 0;
+ end else begin
+ if (we) begin
+ ram_block[addr] = data_write;
+ end
+ data_read = ram_block[addr];
+ end
+
+end
+
+endmodule