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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
| commit | 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 (patch) | |
| tree | b8831bc5ad48d3375a5b05d6d532e2b3e0f2e490 /src/pc_reg.v | |
| parent | deb7d0a6fc76d5250c238d479cf97d4755abef01 (diff) | |
| download | riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.tar.gz riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.zip | |
refactoring, runs now on fpga
Diffstat (limited to 'src/pc_reg.v')
| -rw-r--r-- | src/pc_reg.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/pc_reg.v b/src/pc_reg.v index 9d7600b..91bf85f 100644 --- a/src/pc_reg.v +++ b/src/pc_reg.v @@ -1,15 +1,15 @@ module pc_reg ( input clk, input rstn, + input we, input [31:0] pc_in, + output reg [31:0] pc ); - parameter PC_INITIAL = 32'h0001_0000; - always @ (posedge clk) begin if (!rstn) pc <= PC_INITIAL; else if (we) pc <= pc_in; |