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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 18:30:51 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-04 18:30:51 +0200 |
| commit | f6a55d5faba42120aa900e2514d9ff5d80dfca8b (patch) | |
| tree | c03fd620359c72402876ddb4708663166599b390 /src/logic_unit.v | |
| parent | 14e5e2120e1176ce63f73adddd102934144c0f12 (diff) | |
| download | riscv_cpu-f6a55d5faba42120aa900e2514d9ff5d80dfca8b.tar.gz riscv_cpu-f6a55d5faba42120aa900e2514d9ff5d80dfca8b.zip | |
renamed some signals
Diffstat (limited to 'src/logic_unit.v')
| -rw-r--r-- | src/logic_unit.v | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/logic_unit.v b/src/logic_unit.v index 5ada9c9..85c9137 100644 --- a/src/logic_unit.v +++ b/src/logic_unit.v @@ -1,16 +1,16 @@ module logic_unit #( parameter N = 32 )( - input [N-1:0] A, B, - input [1:0] OP, // 00: AND, 01: OR, 10: XOR - output reg [N-1:0] RESULT + input [N-1:0] lu_src0, lu_src1, + input [1:0] lu_op, // 00: AND, 01: OR, 10: XOR + output reg [N-1:0] lu_result ); always @ (*) begin - case (OP) - 2'b00: RESULT <= A & B; - 2'b01: RESULT <= A | B; - 2'b10: RESULT <= A ^ B; + case (lu_op) + 2'b00: lu_result <= lu_src0 & lu_src1; + 2'b01: lu_result <= lu_src0 | lu_src1; + 2'b10: lu_result <= lu_src0 ^ lu_src1; endcase end |