From f6a55d5faba42120aa900e2514d9ff5d80dfca8b Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Sat, 4 May 2024 18:30:51 +0200 Subject: renamed some signals --- src/logic_unit.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'src/logic_unit.v') diff --git a/src/logic_unit.v b/src/logic_unit.v index 5ada9c9..85c9137 100644 --- a/src/logic_unit.v +++ b/src/logic_unit.v @@ -1,16 +1,16 @@ module logic_unit #( parameter N = 32 )( - input [N-1:0] A, B, - input [1:0] OP, // 00: AND, 01: OR, 10: XOR - output reg [N-1:0] RESULT + input [N-1:0] lu_src0, lu_src1, + input [1:0] lu_op, // 00: AND, 01: OR, 10: XOR + output reg [N-1:0] lu_result ); always @ (*) begin - case (OP) - 2'b00: RESULT <= A & B; - 2'b01: RESULT <= A | B; - 2'b10: RESULT <= A ^ B; + case (lu_op) + 2'b00: lu_result <= lu_src0 & lu_src1; + 2'b01: lu_result <= lu_src0 | lu_src1; + 2'b10: lu_result <= lu_src0 ^ lu_src1; endcase end -- cgit v1.2.3