async reset

1 files changed, 2 insertions, 2 deletions

diff --git a/src/data_reg.v b/src/data_reg.v
index a32a9cf..473d50a 100644
--- a/src/data_reg.v
+++ b/src/data_reg.v
@@ -1,12 +1,12 @@
 module data_reg (
   input clk,
   input rstn,
-  
+
   input [31:0] data_in,
   output reg [31:0] data_buf
 );
 
-always @ (posedge clk) begin
+always @ (posedge clk or negedge rstn) begin
   if (!rstn) data_buf <= 32'b0;
   else data_buf <= data_in;
 end