From 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Mon, 13 May 2024 08:06:30 +0200 Subject: async reset --- src/clock_divider.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/clock_divider.v') diff --git a/src/clock_divider.v b/src/clock_divider.v index 0ece86d..a63e943 100644 --- a/src/clock_divider.v +++ b/src/clock_divider.v @@ -9,7 +9,7 @@ module clock_divider #( reg [31:0] counter = 0; -always @(posedge clk) begin +always @(posedge clk or negedge rstn) begin if (!rstn) begin counter <= 0; clk_div <= 0; -- cgit v1.2.3