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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 08:06:30 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 08:06:30 +0200 |
| commit | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (patch) | |
| tree | c24a7ab1b5f17db28391af6ff8d9c9ccc20bc94e /src/alu_result_reg.v | |
| parent | 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 (diff) | |
| download | riscv_cpu-05366e24d8b3cfca4b856b1b3740d535cbdf7dd7.tar.gz riscv_cpu-05366e24d8b3cfca4b856b1b3740d535cbdf7dd7.zip | |
async reset
Diffstat (limited to 'src/alu_result_reg.v')
| -rw-r--r-- | src/alu_result_reg.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/alu_result_reg.v b/src/alu_result_reg.v index 8de7a08..cece9e4 100644 --- a/src/alu_result_reg.v +++ b/src/alu_result_reg.v @@ -1,12 +1,12 @@ module alu_result_reg ( input clk, input rstn, - + input [31:0] alu_result_in, output reg [31:0] alu_result_buf ); -always @ (posedge clk) begin +always @ (posedge clk or negedge rstn) begin if (!rstn) alu_result_buf <= 32'b0; else alu_result_buf <= alu_result_in; end |