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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 13:50:28 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 13:50:28 +0200
commitcb0be9e2039569ee7d18657e8f675d1f8369b407 (patch)
tree91fa71b3960d1ad5217759371143efbdd833d475 /rtl/src/pc_reg.v
parent98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff)
downloadriscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz
riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip
restructured project
Diffstat (limited to 'rtl/src/pc_reg.v')
-rw-r--r--rtl/src/pc_reg.v18
1 files changed, 18 insertions, 0 deletions
diff --git a/rtl/src/pc_reg.v b/rtl/src/pc_reg.v
new file mode 100644
index 0000000..d8dfbec
--- /dev/null
+++ b/rtl/src/pc_reg.v
@@ -0,0 +1,18 @@
+module pc_reg (
+ input clk,
+ input rstn,
+
+ input we,
+ input [31:0] pc_in,
+
+ output reg [31:0] pc
+);
+
+`include "include/consts.vh"
+
+always @ (posedge clk or negedge rstn) begin
+ if (!rstn) pc <= PC_INITIAL;
+ else if (we) pc <= pc_in;
+end
+
+endmodule