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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
commit | cb0be9e2039569ee7d18657e8f675d1f8369b407 (patch) | |
tree | 91fa71b3960d1ad5217759371143efbdd833d475 /rtl/src/arithmetic_unit.v | |
parent | 98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff) | |
download | riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip |
restructured project
Diffstat (limited to 'rtl/src/arithmetic_unit.v')
-rw-r--r-- | rtl/src/arithmetic_unit.v | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/rtl/src/arithmetic_unit.v b/rtl/src/arithmetic_unit.v new file mode 100644 index 0000000..1a2282b --- /dev/null +++ b/rtl/src/arithmetic_unit.v @@ -0,0 +1,27 @@ +module arithmetic_unit ( + input [31:0] a, + input [31:0] b, + + input [1:0] op, + + output reg [31:0] result +); + +`include "include/consts.vh" + +wire signed [31:0] a_signed, b_signed; + +assign a_signed = a; +assign b_signed = b; + +always @ (*) begin + case (op) + ARITHMETIC_OP_ADD: result = a + b; // ADD + ARITHMETIC_OP_SUB: result = a - b; // SUB + ARITHMETIC_OP_SLT: result = { {31{1'b0}}, a_signed < b_signed }; // SLT + ARITHMETIC_OP_SLTU: result = { {31{1'b0}}, a < b }; // SLTU + default: result = 32'b0; + endcase +end + +endmodule |