align

1 files changed, 4 insertions, 4 deletions

diff --git a/rtl/src/alu_result_reg.v b/rtl/src/alu_result_reg.v
index 377760a..dc78c38 100644
--- a/rtl/src/alu_result_reg.v
+++ b/rtl/src/alu_result_reg.v
@@ -3,16 +3,16 @@
 // This is used for example on load/store, alu wb, etc.
 
 module alu_result_reg (
-  input clk, 
-  input rstn,
+  input             clk, 
+  input             rstn,
 
-  input [31:0] alu_result_in,
+  input      [31:0] alu_result_in,
   output reg [31:0] alu_result_buf
 );
 
 always @ (posedge clk or negedge rstn) begin
   if (!rstn) alu_result_buf <= 32'b0;
-  else alu_result_buf <= alu_result_in;
+  else       alu_result_buf <= alu_result_in;
 end
 
 endmodule