From c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Thu, 23 May 2024 07:04:37 +0200 Subject: align --- rtl/src/alu_result_reg.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'rtl/src/alu_result_reg.v') diff --git a/rtl/src/alu_result_reg.v b/rtl/src/alu_result_reg.v index 377760a..dc78c38 100644 --- a/rtl/src/alu_result_reg.v +++ b/rtl/src/alu_result_reg.v @@ -3,16 +3,16 @@ // This is used for example on load/store, alu wb, etc. module alu_result_reg ( - input clk, - input rstn, + input clk, + input rstn, - input [31:0] alu_result_in, + input [31:0] alu_result_in, output reg [31:0] alu_result_buf ); always @ (posedge clk or negedge rstn) begin if (!rstn) alu_result_buf <= 32'b0; - else alu_result_buf <= alu_result_in; + else alu_result_buf <= alu_result_in; end endmodule -- cgit v1.2.3