From f6a55d5faba42120aa900e2514d9ff5d80dfca8b Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Sat, 4 May 2024 18:30:51 +0200 Subject: renamed some signals --- README.md | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index 1f33d03..34e6d4e 100644 --- a/README.md +++ b/README.md @@ -2,6 +2,10 @@ An attempt at building a simple RISCV CPU in verilog. +## FPGA + +The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html) with a GW1NR-LV9QN88PC6/I5 FPGA. There is a crystal clock onboard running at 27 MHz. + ## Build * `make all` alias for `make simulate`. @@ -10,3 +14,4 @@ An attempt at building a simple RISCV CPU in verilog. * `make program` to upload the bitstream to the FPGA. * `make flash` to flash the bitsream to the FPGA. * `make clean` to clean build files. + -- cgit v1.2.3