From 4a52f5f4699a445c034300c5d292b6e919b924b0 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Tue, 21 May 2024 07:46:21 +0200 Subject: mixed up riscv tables in README --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 96a7d4b..d98e570 100644 --- a/README.md +++ b/README.md @@ -90,8 +90,8 @@ Here we can see the waveforms of various internal signal of the CPU, executing t ### RV32I ISA -![RV32I ISA Table](res/riscv_isa_registers_table.jpg) +![RV32I ISA Table](res/riscv_isa_rv32i_table.jpg) ### Registers -![RV32 Register Table](res/riscv_isa_rv32i_table.jpg) +![RV32 Register Table](res/riscv_isa_registers_table.jpg) -- cgit v1.2.3