| Mode | Name | Size | |
|---|---|---|---|
| -rwxr-xr-x | build.sh | 265 | logplain |
| -rw-r--r-- | link.ld | 353 | logplain |
| -rwxr-xr-x | main.bin | 16 | logplain |
| -rwxr-xr-x | main.elf | 8764 | logplain |
| -rw-r--r-- | main.hex | 48 | logplain |
| -rw-r--r-- | main.o | 4880 | logplain |
| -rw-r--r-- | main.s | 294 | logplain |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |