| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-12 | refactoring | Flavian Kaufmann |
| 2024-05-09 | fixed sw bug, where we wasn't set correctly | Flavian Kaufmann |
| 2024-05-07 | cpu | Flavian Kaufmann |
| 2024-05-05 | initialize rom to rom/rom.hex | Flavian Kaufmann |
| 2024-05-05 | added memory unit | Flavian Kaufmann |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |