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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-09 10:13:14 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-09 10:13:14 +0200 |
| commit | 678aef68af85c04015d8c385f6d6c60ffada7fad (patch) | |
| tree | a36f8af2af4a5485a186084f9ee30fcbdb0c6586 /src/memory_unit.v | |
| parent | 89c0244b8bcd98e8dd273888a0cadc43357f79fc (diff) | |
| download | riscv_cpu-678aef68af85c04015d8c385f6d6c60ffada7fad.tar.gz riscv_cpu-678aef68af85c04015d8c385f6d6c60ffada7fad.zip | |
fixed sw bug, where we wasn't set correctly
Diffstat (limited to 'src/memory_unit.v')
| -rw-r--r-- | src/memory_unit.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/memory_unit.v b/src/memory_unit.v index b2d7434..6e2b457 100644 --- a/src/memory_unit.v +++ b/src/memory_unit.v @@ -13,7 +13,7 @@ wire [31:0] ram_read_data, rom_read_data; ram #(.N(32), .SIZE(1024)) ram( .clk(clk), .rst(rst), - .we(we_ram), + .we(ram_we), .addr(addr), .data_read(ram_read_data), .data_write(write_data) @@ -44,8 +44,8 @@ always @(*) begin read_data <= 0; end else if (addr[31:16] >= 16'h0001 && addr[31:16] <= 16'h000F) begin read_data <= rom_read_data; - ram_we = we; end else if (addr[31:16] >= 16'h0010 && addr[31:16] <= 16'hFF0F) begin + ram_we = we; read_data <= ram_read_data; end else if (addr[31:16] >= 16'hFF10 && addr[31:16] <= 16'hFFFF) begin read_data <= 0; |