1 files changed, 3 insertions, 7 deletions
diff --git a/src/alu.v b/src/alu.v
index 61bb2fb..d54721b 100644
--- a/src/alu.v
+++ b/src/alu.v
@@ -4,8 +4,7 @@ module alu #(
   input [N-1:0] A, B,
   input [3:0] OP, // OP[3:2] 00: ARITHMETIC, 01: LOGIC, 10: SHIFT 
   output reg [N-1:0] RESULT,
-  output ZERO,
-  output OVERFLOW
+  output ZERO
 );
 
 wire [N-1:0] arithmetic_result, logic_result, shift_result;
@@ -14,8 +13,7 @@ arithmetic_unit #(.N(N)) au (
   .A(A),
   .B(B),
   .OP(OP[1:0]),
-  .RESULT(arithmetic_result),
-  .OVERFLOW(overflow)
+  .RESULT(arithmetic_result)
 );
 
 logic_unit #(.N(N)) lu (
@@ -27,7 +25,7 @@ logic_unit #(.N(N)) lu (
 
 shift_unit #(.N(N)) su (
   .A(A),
-  .SHAMT(B[clog2(N):0]),
+  .SHAMT(B),
   .OP(OP[1:0]),
   .RESULT(shift_result)
 );
@@ -40,8 +38,6 @@ always @ (*) begin
   endcase
 end
 
-assign OVERFLOW = OP[3:2] == 2'b00 ? overflow : 0;
-
 assign ZERO = ~|RESULT;
 
 endmodule