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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:08:53 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 16:08:53 +0200 |
| commit | ca5a25cfbdbefada9dfb94a097b65e69226f3f9a (patch) | |
| tree | cc9598ea41947b1e4cf008f430fc56e1c727d968 /src/alu.v | |
| parent | 51b0a4c850fbf0ed70abe694be143b2b10e3e578 (diff) | |
| download | riscv_cpu-ca5a25cfbdbefada9dfb94a097b65e69226f3f9a.tar.gz riscv_cpu-ca5a25cfbdbefada9dfb94a097b65e69226f3f9a.zip | |
fixed alu bugs
Diffstat (limited to 'src/alu.v')
| -rw-r--r-- | src/alu.v | 10 |
1 files changed, 3 insertions, 7 deletions
@@ -4,8 +4,7 @@ module alu #( input [N-1:0] A, B, input [3:0] OP, // OP[3:2] 00: ARITHMETIC, 01: LOGIC, 10: SHIFT output reg [N-1:0] RESULT, - output ZERO, - output OVERFLOW + output ZERO ); wire [N-1:0] arithmetic_result, logic_result, shift_result; @@ -14,8 +13,7 @@ arithmetic_unit #(.N(N)) au ( .A(A), .B(B), .OP(OP[1:0]), - .RESULT(arithmetic_result), - .OVERFLOW(overflow) + .RESULT(arithmetic_result) ); logic_unit #(.N(N)) lu ( @@ -27,7 +25,7 @@ logic_unit #(.N(N)) lu ( shift_unit #(.N(N)) su ( .A(A), - .SHAMT(B[clog2(N):0]), + .SHAMT(B), .OP(OP[1:0]), .RESULT(shift_result) ); @@ -40,8 +38,6 @@ always @ (*) begin endcase end -assign OVERFLOW = OP[3:2] == 2'b00 ? overflow : 0; - assign ZERO = ~|RESULT; endmodule |