1 files changed, 54 insertions, 14 deletions
diff --git a/sim/testbench.v b/sim/testbench.v
index 6221b01..5a47111 100644
--- a/sim/testbench.v
+++ b/sim/testbench.v
@@ -1,26 +1,66 @@
-module testbench;
+`timescale 1ns / 1ps
+
+module testbench();
 
   reg reset = 0;
+  
   initial begin
     $dumpfile("testbench.vcd");
     $dumpvars(0,testbench);
-
-    # 17 reset = 1;
-    # 11 reset = 0;
-    # 29 reset = 1;
-    # 5  reset = 0;
-    # 128 $finish;
   end
 
   reg clk = 0;
-  always #1 clk = !clk;
+  always #32 clk = !clk;
+
+
+  reg [31:0] a, b, exp_result;
+  reg [3:0] op;
+  reg [3:0] exp_flags;
+  wire [31:0] result;
+  wire zero, exp_zero;
+
+  assign exp_zero = exp_flags[0];
+
+  reg [31:0]	vector_count, error_count;
+  reg [103:0] testvec [0:9999];
+
+  initial begin
+    $readmemh("alu_testvec.txt", testvec);
+    error_count = 0;
+    vector_count = 0;
+  end
+  
+  always @ (posedge clk) begin
+    #16;
+    {op, a, b, exp_result, exp_flags} = testvec[vector_count];
+    #32;
+    if ((result !== exp_result) | (zero !== exp_zero)) begin
+      $display("Error at %5d ns: op %b a = %h b = %h", $time, op, a, b);
+      $display("       %h (expected %h)", result, exp_result);
+      $display(" zero: %b (expected %b)", zero, exp_zero);
+
+      error_count = error_count + 1;
+    end
+
+    vector_count = vector_count + 1;
+
+    if ((vector_count == 9027)) begin
+      $display("%d tests completed with %d errors", vector_count, error_count);
+      #16;
+
+      $finish;
+    end
+  end
 
-  wire [5:0] led;
-  wire reset_inv;
-  assign reset_inv = ~reset;
-  top blinky(.clk(clk), .key(reset_inv), .led(led));
+  
+  
 
-  initial
-     $monitor("At time %t, value = %h (%0d)", $time, led, led);
+  alu #(.N(32)) alu (
+    .A(a),
+    .B(b),
+    .OP(op),
+    .RESULT(result),
+    .ZERO(zero)
+  );
 
 endmodule