aboutsummaryrefslogtreecommitdiff
path: root/src/rom.v
diff options
context:
space:
mode:
authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-13 07:46:45 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-13 07:46:45 +0200
commit48205bf3e8d421b6aa0474a4d120ae5faaaaa670 (patch)
treeb8831bc5ad48d3375a5b05d6d532e2b3e0f2e490 /src/rom.v
parentdeb7d0a6fc76d5250c238d479cf97d4755abef01 (diff)
downloadriscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.tar.gz
riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.zip
refactoring, runs now on fpga
Diffstat (limited to 'src/rom.v')
-rw-r--r--src/rom.v2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/rom.v b/src/rom.v
index 8a25f46..381ca64 100644
--- a/src/rom.v
+++ b/src/rom.v
@@ -17,6 +17,4 @@ end
assign data_read = {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
-
-
endmodule