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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
commit | cb0be9e2039569ee7d18657e8f675d1f8369b407 (patch) | |
tree | 91fa71b3960d1ad5217759371143efbdd833d475 /src/register_file_reg.v | |
parent | 98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff) | |
download | riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip |
restructured project
Diffstat (limited to 'src/register_file_reg.v')
-rw-r--r-- | src/register_file_reg.v | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/register_file_reg.v b/src/register_file_reg.v deleted file mode 100644 index b1bd4fc..0000000 --- a/src/register_file_reg.v +++ /dev/null @@ -1,22 +0,0 @@ -module register_file_reg ( - input clk, - input rstn, - - input [31:0] rd1_in, - input [31:0] rd2_in, - - output reg [31:0] rd1_buf, - output reg [31:0] rd2_buf -); - -always @ (posedge clk or negedge rstn) begin - if (!rstn) begin - rd1_buf <= 32'b0; - rd2_buf <= 32'b0; - end else begin - rd1_buf <= rd1_in; - rd2_buf <= rd2_in; - end -end - -endmodule |