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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 08:06:30 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 08:06:30 +0200 |
| commit | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (patch) | |
| tree | c24a7ab1b5f17db28391af6ff8d9c9ccc20bc94e /src/register_file_reg.v | |
| parent | 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 (diff) | |
| download | riscv_cpu-05366e24d8b3cfca4b856b1b3740d535cbdf7dd7.tar.gz riscv_cpu-05366e24d8b3cfca4b856b1b3740d535cbdf7dd7.zip | |
async reset
Diffstat (limited to 'src/register_file_reg.v')
| -rw-r--r-- | src/register_file_reg.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/register_file_reg.v b/src/register_file_reg.v index 20222d7..b1bd4fc 100644 --- a/src/register_file_reg.v +++ b/src/register_file_reg.v @@ -9,7 +9,7 @@ module register_file_reg ( output reg [31:0] rd2_buf ); -always @ (posedge clk) begin +always @ (posedge clk or negedge rstn) begin if (!rstn) begin rd1_buf <= 32'b0; rd2_buf <= 32'b0; |