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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-20 11:39:26 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-20 11:39:26 +0200 |
commit | 407a3ff54a35cbe99ba6ac743376e9b0e9718fc1 (patch) | |
tree | b96527b0b55bb63e21551f9a93d3c3271dd39988 /src/register_file.v | |
parent | def3f62f7f8d6b5bd4b15500c7d11935540e81da (diff) | |
download | riscv_cpu-407a3ff54a35cbe99ba6ac743376e9b0e9718fc1.tar.gz riscv_cpu-407a3ff54a35cbe99ba6ac743376e9b0e9718fc1.zip |
nextpnr himbaechel
Diffstat (limited to 'src/register_file.v')
-rw-r--r-- | src/register_file.v | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/register_file.v b/src/register_file.v index 7f83704..dda44e8 100644 --- a/src/register_file.v +++ b/src/register_file.v @@ -10,9 +10,7 @@ module register_file ( input [31:0] wd3, output [31:0] rd1, - output [31:0] rd2, - - output [31:0] dbg_t6 + output [31:0] rd2 ); reg [31:0] regs[31:1]; @@ -84,8 +82,6 @@ assign reg_x29_t4 = regs[29]; assign reg_x30_t5 = regs[30]; assign reg_x31_t6 = regs[31]; -assign dbg_t6 = reg_x31_t6; - assign rd1 = ra1 == 0 ? 32'b0 : regs[ra1]; assign rd2 = ra2 == 0 ? 32'b0 : regs[ra2]; |