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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-09 11:26:33 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-09 11:26:33 +0200
commit008059fbe4e960a10bb4c444013129e0aaa02818 (patch)
tree0e37db7e4ac82fc33c86e5f1dcaa0de59e983c73 /src/ram.v
parentd810d1cd42a31268ccb33993f1f1f429900c5ff8 (diff)
downloadriscv_cpu-008059fbe4e960a10bb4c444013129e0aaa02818.tar.gz
riscv_cpu-008059fbe4e960a10bb4c444013129e0aaa02818.zip
stopped initializing ram and register file to 0 at beginning
Diffstat (limited to 'src/ram.v')
-rw-r--r--src/ram.v14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/ram.v b/src/ram.v
index 9b62c77..efcfc04 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -17,16 +17,16 @@ reg [8:0] memory [SIZE-1:0];
assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
-integer i;
-always @(posedge clk or posedge rst) begin
- if (rst) begin
- for (i = 0; i < SIZE; i = i + 1)
- memory[i] <= 0;
- end else begin
+// integer i;
+always @(posedge clk /*or posedge rst*/) begin
+// if (rst) begin
+// for (i = 0; i < SIZE; i = i + 1)
+// memory[i] <= 0;
+// end else begin
if (we) begin
{ memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
end
- end
+// end
end