fixed sw bug, where we wasn't set correctly

1 files changed, 5 insertions, 3 deletions

diff --git a/src/ram.v b/src/ram.v
index 92b14a2..9b62c77 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -7,23 +7,25 @@ module ram #(
     input we,
     input [log2(SIZE)-1:0] addr,
     input [N-1:0] data_write,
-    output reg [N-1:0] data_read
+    output [N-1:0] data_read
 );
 
 `include "include/log2.vh"
 
 reg [8:0] memory [SIZE-1:0];
 
+assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
+
+
 integer i;
 always @(posedge clk or posedge rst) begin
   if (rst) begin
     for (i = 0; i < SIZE; i = i + 1)
       memory[i] <= 0;
-  end else begin
+  end else begin 
     if (we) begin
       { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
     end
-    data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
   end
 
 end