From 678aef68af85c04015d8c385f6d6c60ffada7fad Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Thu, 9 May 2024 10:13:14 +0200 Subject: fixed sw bug, where we wasn't set correctly --- src/ram.v | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/ram.v') diff --git a/src/ram.v b/src/ram.v index 92b14a2..9b62c77 100644 --- a/src/ram.v +++ b/src/ram.v @@ -7,23 +7,25 @@ module ram #( input we, input [log2(SIZE)-1:0] addr, input [N-1:0] data_write, - output reg [N-1:0] data_read + output [N-1:0] data_read ); `include "include/log2.vh" reg [8:0] memory [SIZE-1:0]; +assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] }; + + integer i; always @(posedge clk or posedge rst) begin if (rst) begin for (i = 0; i < SIZE; i = i + 1) memory[i] <= 0; - end else begin + end else begin if (we) begin { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write; end - data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] }; end end -- cgit v1.2.3