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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
| commit | 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 (patch) | |
| tree | b8831bc5ad48d3375a5b05d6d532e2b3e0f2e490 /src/memory_interface.v | |
| parent | deb7d0a6fc76d5250c238d479cf97d4755abef01 (diff) | |
| download | riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.tar.gz riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.zip | |
refactoring, runs now on fpga
Diffstat (limited to 'src/memory_interface.v')
| -rw-r--r-- | src/memory_interface.v | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/memory_interface.v b/src/memory_interface.v index 0b89e39..0ea837a 100644 --- a/src/memory_interface.v +++ b/src/memory_interface.v @@ -1,16 +1,18 @@ module memory_interface ( input clk, input rstn, + input we, input [31:0] addr, - output reg [31:0] rd, - input [31:0] wd + input [31:0] wd, + + output reg [31:0] rd ); reg ram_we; wire [31:0] ram_read_data, rom_read_data; -ram #(.N(32), .SIZE(1024)) ram( +ram #(.N(32), .SIZE(16)) ram( .clk(clk), .rst(!rstn), .we(ram_we), @@ -19,7 +21,7 @@ ram #(.N(32), .SIZE(1024)) ram( .data_write(wd) ); -rom #(.N(32), .SIZE(1024)) rom( +rom #(.N(32), .SIZE(32)) rom( .clk(clk), .addr(addr), .data_read(rom_read_data) |