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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-14 10:38:47 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-14 10:38:47 +0200 |
| commit | d107f7e40f02a7374b8685ba310500a6c38d43b1 (patch) | |
| tree | 55615eaface31b2473be3dae90fe822c5373f492 /src/mem_addr_src_mux.v | |
| parent | 48b36fddef862c3cd5efbdd3ed3e86b179ac117b (diff) | |
| download | riscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.tar.gz riscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.zip | |
bug fixes
Diffstat (limited to 'src/mem_addr_src_mux.v')
| -rw-r--r-- | src/mem_addr_src_mux.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem_addr_src_mux.v b/src/mem_addr_src_mux.v index 633b345..1f34fe1 100644 --- a/src/mem_addr_src_mux.v +++ b/src/mem_addr_src_mux.v @@ -11,9 +11,9 @@ module mem_addr_src_mux ( always @(*) begin case (mem_addr_src) - MEM_ADDR_SRC_PC: mem_addr <= src_pc; - MEM_ADDR_SRC_RESULT: mem_addr <= src_result; - default: mem_addr <= 32'b0; + MEM_ADDR_SRC_PC: mem_addr = src_pc; + MEM_ADDR_SRC_RESULT: mem_addr = src_result; + default: mem_addr = 32'b0; endcase end |