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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
| commit | 9c7d7fd782f70d99120ce6ac45a897606b52c878 (patch) | |
| tree | a6f36fed8ec3e42e08d51afee500190af8194df4 /src/mem_addr_src_mux.v | |
| parent | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (diff) | |
| download | riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.tar.gz riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.zip | |
refactoring constants
Diffstat (limited to 'src/mem_addr_src_mux.v')
| -rw-r--r-- | src/mem_addr_src_mux.v | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mem_addr_src_mux.v b/src/mem_addr_src_mux.v index c5c64f0..633b345 100644 --- a/src/mem_addr_src_mux.v +++ b/src/mem_addr_src_mux.v @@ -7,11 +7,13 @@ module mem_addr_src_mux ( output reg [31:0] mem_addr ); +`include "include/consts.vh" + always @(*) begin case (mem_addr_src) - 1'b0: mem_addr <= src_pc; - 1'b1: mem_addr <= src_result; - default: mem_addr <= 32'b0; + MEM_ADDR_SRC_PC: mem_addr <= src_pc; + MEM_ADDR_SRC_RESULT: mem_addr <= src_result; + default: mem_addr <= 32'b0; endcase end |