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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-05 10:27:21 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-05 10:27:21 +0200 |
| commit | 8d5d730269cc94fa8d5caed0e1996e3d94be25d1 (patch) | |
| tree | 73154eacc2c7483a24aecd05a984638ff322d5d6 /src/logic_unit.v | |
| parent | f6a55d5faba42120aa900e2514d9ff5d80dfca8b (diff) | |
| download | riscv_cpu-8d5d730269cc94fa8d5caed0e1996e3d94be25d1.tar.gz riscv_cpu-8d5d730269cc94fa8d5caed0e1996e3d94be25d1.zip | |
added register file
Diffstat (limited to 'src/logic_unit.v')
| -rw-r--r-- | src/logic_unit.v | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/logic_unit.v b/src/logic_unit.v index 85c9137..0bbd642 100644 --- a/src/logic_unit.v +++ b/src/logic_unit.v @@ -1,17 +1,17 @@ module logic_unit #( parameter N = 32 )( - input [N-1:0] lu_src0, lu_src1, - input [1:0] lu_op, // 00: AND, 01: OR, 10: XOR - output reg [N-1:0] lu_result + input [N-1:0] src0, src1, + input [1:0] op, // 00: AND, 01: OR, 10: XOR + output reg [N-1:0] result ); - always @ (*) begin - case (lu_op) - 2'b00: lu_result <= lu_src0 & lu_src1; - 2'b01: lu_result <= lu_src0 | lu_src1; - 2'b10: lu_result <= lu_src0 ^ lu_src1; - endcase - end +always @ (*) begin + case (op) + 2'b00: result <= src0 & src1; + 2'b01: result <= src0 | src1; + 2'b10: result <= src0 ^ src1; + endcase +end endmodule |