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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 07:46:45 +0200 |
| commit | 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 (patch) | |
| tree | b8831bc5ad48d3375a5b05d6d532e2b3e0f2e490 /src/logic_unit.v | |
| parent | deb7d0a6fc76d5250c238d479cf97d4755abef01 (diff) | |
| download | riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.tar.gz riscv_cpu-48205bf3e8d421b6aa0474a4d120ae5faaaaa670.zip | |
refactoring, runs now on fpga
Diffstat (limited to 'src/logic_unit.v')
| -rw-r--r-- | src/logic_unit.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/logic_unit.v b/src/logic_unit.v index f9f62a2..c717f23 100644 --- a/src/logic_unit.v +++ b/src/logic_unit.v @@ -1,6 +1,9 @@ module logic_unit ( - input [31:0] a, b, + input [31:0] a, + input [31:0] b, + input [1:0] op, + output reg [31:0] result ); |