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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
commit | 9c7d7fd782f70d99120ce6ac45a897606b52c878 (patch) | |
tree | a6f36fed8ec3e42e08d51afee500190af8194df4 /src/cpu.v | |
parent | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (diff) | |
download | riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.tar.gz riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.zip |
refactoring constants
Diffstat (limited to 'src/cpu.v')
-rw-r--r-- | src/cpu.v | 12 |
1 files changed, 8 insertions, 4 deletions
@@ -19,7 +19,10 @@ control_unit control_unit ( .alu_op(alu_op), .alu_a_src(alu_a_src), .alu_b_src(alu_b_src), - .rf_we(rf_we) + .rf_we(rf_we), + .ra1(ra1), + .ra2(ra2), + .wa3(wa3) ); @@ -40,6 +43,7 @@ wire [2:0] imm_src; wire [31:0] data_buf; wire rf_we; +wire [4:0] ra1, ra2, wa3; wire [31:0] rd1, rd2; wire [31:0] rd1_buf, rd2_buf; @@ -106,9 +110,9 @@ register_file register_file ( .clk(clk), .rstn(rstn), .we(rf_we), - .ra1(instr[19:15]), - .ra2(instr[24:20]), - .wa3(instr[11:7]), + .ra1(ra1), + .ra2(ra2), + .wa3(wa3), .rd1(rd1), .rd2(rd2), .wd3(result), |