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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
| commit | 9c7d7fd782f70d99120ce6ac45a897606b52c878 (patch) | |
| tree | a6f36fed8ec3e42e08d51afee500190af8194df4 /src/arithmetic_unit.v | |
| parent | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (diff) | |
| download | riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.tar.gz riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.zip | |
refactoring constants
Diffstat (limited to 'src/arithmetic_unit.v')
| -rw-r--r-- | src/arithmetic_unit.v | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v index 261b526..2ac302e 100644 --- a/src/arithmetic_unit.v +++ b/src/arithmetic_unit.v @@ -7,6 +7,8 @@ module arithmetic_unit ( output reg [31:0] result ); +`include "include/consts.vh" + wire signed [31:0] a_signed, b_signed; assign a_signed = a; @@ -14,10 +16,11 @@ assign b_signed = b; always @ (*) begin case (op) - 2'b00: result <= a + b; // ADD - 2'b01: result <= a - b; // SUB - 2'b10: result <= { {31{1'b0}}, a_signed < b_signed }; // SLT - 2'b11: result <= { {31{1'b0}}, a < b }; // SLTU + ARITHMETIC_OP_ADD: result <= a + b; // ADD + ARITHMETIC_OP_SUB: result <= a - b; // SUB + ARITHMETIC_OP_SLT: result <= { {31{1'b0}}, a_signed < b_signed }; // SLT + ARITHMETIC_OP_SLTU: result <= { {31{1'b0}}, a < b }; // SLTU + default: result <= 32'b0; endcase end |