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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 12:40:49 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 12:40:49 +0200 |
commit | 766273a6a50d57777e455d07a015300255becb6d (patch) | |
tree | e283ed5c50a9c8af7d0624c0bc7440b0ccda0af9 /src/arithmetic_unit.v | |
parent | 1ee5fc13995ee1383b0b75a19003b08fe33cfa54 (diff) | |
download | riscv_cpu-766273a6a50d57777e455d07a015300255becb6d.tar.gz riscv_cpu-766273a6a50d57777e455d07a015300255becb6d.zip |
alu
Diffstat (limited to 'src/arithmetic_unit.v')
-rw-r--r-- | src/arithmetic_unit.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v new file mode 100644 index 0000000..be087a7 --- /dev/null +++ b/src/arithmetic_unit.v @@ -0,0 +1,24 @@ +module arithmetic_unit #( + parameter N = 32 +)( + input [N-1:0] A, B, + input [1:0] OP, // 00: ADD, 01: SUB, 11: SLT + output [N-1:0] RESULT, + output OVERFLOW +); + +wire [N-1:0] b, sum; +wire cin, altb; + +assign b = OP[0] ? ~B : B; +assign cin = OP[0]; + +assign sum = A + b + cin; + +assign OVERFLOW = ~(A[N-1] ^ B[N-1] ^ OP[0]) & (A[N-1] ^ sum[N-1]); + +assign altb = OVERFLOW ^ sum[N-1]; + +assign RESULT = OP[1] ? {{(N-1){1'b0}}, altb} : sum; + +endmodule |