diff options
| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
| commit | 9c7d7fd782f70d99120ce6ac45a897606b52c878 (patch) | |
| tree | a6f36fed8ec3e42e08d51afee500190af8194df4 /src/alu_b_src_mux.v | |
| parent | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (diff) | |
| download | riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.tar.gz riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.zip | |
refactoring constants
Diffstat (limited to 'src/alu_b_src_mux.v')
| -rw-r--r-- | src/alu_b_src_mux.v | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/alu_b_src_mux.v b/src/alu_b_src_mux.v index 99dffab..615d312 100644 --- a/src/alu_b_src_mux.v +++ b/src/alu_b_src_mux.v @@ -7,12 +7,14 @@ module alu_b_src_mux ( output reg [31:0] alu_b ); +`include "include/consts.vh" + always @(*) begin case (alu_b_src) - 2'b00: alu_b <= src_rd2_buf; - 2'b01: alu_b <= src_imm; - 2'b10: alu_b <= 32'h4; - default: alu_b <= 32'b0; + ALU_B_SRC_RD2_BUF: alu_b <= src_rd2_buf; + ALU_B_SRC_IMM: alu_b <= src_imm; + ALU_B_SRC_4: alu_b <= 32'h4; + default: alu_b <= 32'b0; endcase end |