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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 07:28:34 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 07:28:34 +0200 |
| commit | 9f1ab1f834c58c231617f3be12f16793061d4630 (patch) | |
| tree | dfb5040d4568010ecc765dee61f1ade9a4d7fc02 /src/alu_a_src_mux.v | |
| parent | 5a549e61af1df0c4016f00af830120d21a88a0e7 (diff) | |
| download | riscv_cpu-9f1ab1f834c58c231617f3be12f16793061d4630.tar.gz riscv_cpu-9f1ab1f834c58c231617f3be12f16793061d4630.zip | |
cleaned up graphics
Diffstat (limited to 'src/alu_a_src_mux.v')
| -rw-r--r-- | src/alu_a_src_mux.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/alu_a_src_mux.v b/src/alu_a_src_mux.v index 8998b55..fef701b 100644 --- a/src/alu_a_src_mux.v +++ b/src/alu_a_src_mux.v @@ -1,8 +1,8 @@ module alu_a_src_mux ( input [31:0] src_pc, - input [31:0] src_pc_buf, - input [31:0] src_rd1_buf, + input [31:0] src_pc_buf, input [31:0] src_rd1, + input [31:0] src_rd1_buf, input [2:0] alu_a_src, @@ -15,8 +15,8 @@ always @(*) begin case (alu_a_src) ALU_A_SRC_PC: alu_a = src_pc; ALU_A_SRC_PC_BUF: alu_a = src_pc_buf; - ALU_A_SRC_RD1_BUF: alu_a = src_rd1_buf; ALU_A_SRC_RD1: alu_a = src_rd1; + ALU_A_SRC_RD1_BUF: alu_a = src_rd1_buf; ALU_A_SRC_0: alu_a = 32'b0; default: alu_a = 32'b0; endcase |