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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
| commit | 9c7d7fd782f70d99120ce6ac45a897606b52c878 (patch) | |
| tree | a6f36fed8ec3e42e08d51afee500190af8194df4 /src/alu_a_src_mux.v | |
| parent | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (diff) | |
| download | riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.tar.gz riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.zip | |
refactoring constants
Diffstat (limited to 'src/alu_a_src_mux.v')
| -rw-r--r-- | src/alu_a_src_mux.v | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/alu_a_src_mux.v b/src/alu_a_src_mux.v index b51dd5b..208cc82 100644 --- a/src/alu_a_src_mux.v +++ b/src/alu_a_src_mux.v @@ -8,12 +8,15 @@ module alu_a_src_mux ( output reg [31:0] alu_a ); +`include "include/consts.vh" + always @(*) begin case (alu_a_src) - 2'b00: alu_a <= src_pc; - 2'b01: alu_a <= src_pc_buf; - 2'b10: alu_a <= src_rd1_buf; - default: alu_a <= 32'b0; + ALU_A_SRC_PC: alu_a <= src_pc; + ALU_A_SRC_PC_BUF: alu_a <= src_pc_buf; + ALU_A_SRC_RD1_BUF: alu_a <= src_rd1_buf; + ALU_A_SRC_0: alu_a <= 32'b0; + default: alu_a <= 32'b0; endcase end |