alu equal

1 files changed, 3 insertions, 1 deletions

diff --git a/src/alu.v b/src/alu.v
index 6962129..6f9251c 100644
--- a/src/alu.v
+++ b/src/alu.v
@@ -2,7 +2,8 @@ module alu (
   input [31:0] a, b,
   input [3:0] op,
   output reg [31:0] result,
-  output zero
+  output zero,
+  output equal
 );
 
 wire [31:0] arithmetic_result, logic_result, shift_result;
@@ -38,5 +39,6 @@ always @ (*) begin
 end
 
 assign zero = result == 32'b0;
+assign equal = a == b;
 
 endmodule