From 9a357b3ad679751bc7a9ce85adbc303130211226 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Tue, 7 May 2024 21:27:21 +0200 Subject: alu equal --- src/alu.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/alu.v') diff --git a/src/alu.v b/src/alu.v index 6962129..6f9251c 100644 --- a/src/alu.v +++ b/src/alu.v @@ -2,7 +2,8 @@ module alu ( input [31:0] a, b, input [3:0] op, output reg [31:0] result, - output zero + output zero, + output equal ); wire [31:0] arithmetic_result, logic_result, shift_result; @@ -38,5 +39,6 @@ always @ (*) begin end assign zero = result == 32'b0; +assign equal = a == b; endmodule -- cgit v1.2.3