diff options
author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 12:40:49 +0200 |
---|---|---|
committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-01 12:40:49 +0200 |
commit | 766273a6a50d57777e455d07a015300255becb6d (patch) | |
tree | e283ed5c50a9c8af7d0624c0bc7440b0ccda0af9 /src/alu.v | |
parent | 1ee5fc13995ee1383b0b75a19003b08fe33cfa54 (diff) | |
download | riscv_cpu-766273a6a50d57777e455d07a015300255becb6d.tar.gz riscv_cpu-766273a6a50d57777e455d07a015300255becb6d.zip |
alu
Diffstat (limited to 'src/alu.v')
-rw-r--r-- | src/alu.v | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/alu.v b/src/alu.v new file mode 100644 index 0000000..61bb2fb --- /dev/null +++ b/src/alu.v @@ -0,0 +1,47 @@ +module alu #( + parameter N = 32 +)( + input [N-1:0] A, B, + input [3:0] OP, // OP[3:2] 00: ARITHMETIC, 01: LOGIC, 10: SHIFT + output reg [N-1:0] RESULT, + output ZERO, + output OVERFLOW +); + +wire [N-1:0] arithmetic_result, logic_result, shift_result; + +arithmetic_unit #(.N(N)) au ( + .A(A), + .B(B), + .OP(OP[1:0]), + .RESULT(arithmetic_result), + .OVERFLOW(overflow) +); + +logic_unit #(.N(N)) lu ( + .A(A), + .B(B), + .OP(OP[1:0]), + .RESULT(logic_result) +); + +shift_unit #(.N(N)) su ( + .A(A), + .SHAMT(B[clog2(N):0]), + .OP(OP[1:0]), + .RESULT(shift_result) +); + +always @ (*) begin + case (OP[3:2]) + 2'b00: RESULT <= arithmetic_result; + 2'b01: RESULT <= logic_result; + 2'b10: RESULT <= shift_result; + endcase +end + +assign OVERFLOW = OP[3:2] == 2'b00 ? overflow : 0; + +assign ZERO = ~|RESULT; + +endmodule |