| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | .gitignore | 6 | logplain |
| -rw-r--r-- | Makefile | 5253 | logplain |
| -rw-r--r-- | README.md | 848 | logplain |
| d--------- | cst | 42 | logplain |
| d--------- | debug | 36 | logplain |
| d--------- | gentestvec | 142 | logplain |
| d--------- | include | 35 | logplain |
| d--------- | prog | 65 | logplain |
| d--------- | sim | 139 | logplain |
| d--------- | src | 550 | logplain |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |