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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
| commit | cb0be9e2039569ee7d18657e8f675d1f8369b407 (patch) | |
| tree | 91fa71b3960d1ad5217759371143efbdd833d475 /sim/testbenches/Makefile | |
| parent | 98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff) | |
| download | riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip | |
restructured project
Diffstat (limited to 'sim/testbenches/Makefile')
| -rw-r--r-- | sim/testbenches/Makefile | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/sim/testbenches/Makefile b/sim/testbenches/Makefile new file mode 100644 index 0000000..67c8f92 --- /dev/null +++ b/sim/testbenches/Makefile @@ -0,0 +1,42 @@ +BUILD_DIR ?= build +RTL_SOURCES ?= $(wildcard ../../rtl/src/*.v) +TESTVEC_DIR ?= ../../build +INCLUDE = ../../rtl + +TESTVECS ?= $(wildcard $(TESTVEC_DIR)/testvec_*.txt) + +# tools +IVERILOG = iverilog +VVP = vvp +GTKWAVE = gtkwave + +# dirs and files +SOURCE_DIR = src +SOURCES = $(wildcard $(SOURCE_DIR)/*.v) +WAVEFORMS = $(patsubst testvec_%, $(BUILD_DIR)/waveform_%.vcd, $(basename $(notdir $(TESTVECS)))) + + +# targets +all: $(WAVEFORMS) + +# generate testbenches +$(BUILD_DIR)/testbench_%: $(SOURCE_DIR)/testbench_%.v $(RTL_SOURCES) | $(BUILD_DIR) always + $(IVERILOG) -I $(INCLUDE) -o $@ $^ + +# run testbenches +$(BUILD_DIR)/waveform_%.vcd: $(BUILD_DIR)/testbench_% always + $(VVP) $< +testvec=$(shell realpath $(TESTVEC_DIR)/testvec_$*.txt) +waveform=$@ + +$(BUILD_DIR): + mkdir -p $(BUILD_DIR) + +wave: all + $(GTKWAVE) -a ../../debug/cpu.gtkw $(BUILD_DIR)/waveform_cpu.vcd > /dev/null 2>&1 & disown + +# dummy target, s.t. other targets will always be run +always: + +clean: + rm -rf $(BUILD_DIR) + +.PHONY: all clean always
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