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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-05 10:27:21 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-05 10:27:21 +0200 |
| commit | 8d5d730269cc94fa8d5caed0e1996e3d94be25d1 (patch) | |
| tree | 73154eacc2c7483a24aecd05a984638ff322d5d6 /sim/testbench_alu.v | |
| parent | f6a55d5faba42120aa900e2514d9ff5d80dfca8b (diff) | |
| download | riscv_cpu-8d5d730269cc94fa8d5caed0e1996e3d94be25d1.tar.gz riscv_cpu-8d5d730269cc94fa8d5caed0e1996e3d94be25d1.zip | |
added register file
Diffstat (limited to 'sim/testbench_alu.v')
| -rw-r--r-- | sim/testbench_alu.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/sim/testbench_alu.v b/sim/testbench_alu.v index 068efc3..45cce1b 100644 --- a/sim/testbench_alu.v +++ b/sim/testbench_alu.v @@ -76,11 +76,11 @@ module testbench_alu(); alu #(.N(32)) alu ( - .alu_src0(a), - .alu_src1(b), - .alu_op(op), - .alu_result(result), - .alu_zero(zero) + .src0(a), + .src1(b), + .op(op), + .result(result), + .zero(zero) ); endmodule |