From 8d5d730269cc94fa8d5caed0e1996e3d94be25d1 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Sun, 5 May 2024 10:27:21 +0200 Subject: added register file --- sim/testbench_alu.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'sim/testbench_alu.v') diff --git a/sim/testbench_alu.v b/sim/testbench_alu.v index 068efc3..45cce1b 100644 --- a/sim/testbench_alu.v +++ b/sim/testbench_alu.v @@ -76,11 +76,11 @@ module testbench_alu(); alu #(.N(32)) alu ( - .alu_src0(a), - .alu_src1(b), - .alu_op(op), - .alu_result(result), - .alu_zero(zero) + .src0(a), + .src1(b), + .op(op), + .result(result), + .zero(zero) ); endmodule -- cgit v1.2.3