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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
| commit | c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 (patch) | |
| tree | a000085f4ce8d6dec3e90ecc230642eeb77d960f /rtl/src/top.v | |
| parent | ee94c97e4f8208d0c7404887cda16d00f67c6f1f (diff) | |
| download | riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.tar.gz riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.zip | |
align
Diffstat (limited to 'rtl/src/top.v')
| -rw-r--r-- | rtl/src/top.v | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/rtl/src/top.v b/rtl/src/top.v index d21f807..02ab48c 100644 --- a/rtl/src/top.v +++ b/rtl/src/top.v @@ -2,14 +2,13 @@ // Top module, maps signals to fpga. module top ( - input clk, - input key, - input rst, + input clk, + input s1, s2, output [5:0] led ); -wire rstn, rstn_async, clk_cpu; -assign rstn_async = rst; +wire rstn, rstn_async, clk_cpu; +assign rstn_async = s1; wire [31:0] io_in; wire [31:0] io_out; @@ -28,7 +27,7 @@ clock_divider #(.N(1)) clkdiv ( assign led[0] = ~clk_cpu; assign led[5:1] = ~io_out[4:0]; -assign io_in[0] = key; +assign io_in[0] = ~s2; cpu cpu ( |