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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
| commit | c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 (patch) | |
| tree | a000085f4ce8d6dec3e90ecc230642eeb77d960f /rtl/src/shift_unit.v | |
| parent | ee94c97e4f8208d0c7404887cda16d00f67c6f1f (diff) | |
| download | riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.tar.gz riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.zip | |
align
Diffstat (limited to 'rtl/src/shift_unit.v')
| -rw-r--r-- | rtl/src/shift_unit.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/rtl/src/shift_unit.v b/rtl/src/shift_unit.v index 7dbe4a2..5a1dfc4 100644 --- a/rtl/src/shift_unit.v +++ b/rtl/src/shift_unit.v @@ -3,11 +3,11 @@ module shift_unit ( input signed [31:0] a, - input [4:0] b, + input [4:0] b, - input [1:0] op, + input [1:0] op, - output reg [31:0] result + output reg [31:0] result ); `include "include/consts.vh" |