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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
commit | c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 (patch) | |
tree | a000085f4ce8d6dec3e90ecc230642eeb77d960f /rtl/src/rom.v | |
parent | ee94c97e4f8208d0c7404887cda16d00f67c6f1f (diff) | |
download | riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.tar.gz riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.zip |
align
Diffstat (limited to 'rtl/src/rom.v')
-rw-r--r-- | rtl/src/rom.v | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/rtl/src/rom.v b/rtl/src/rom.v index f32b9a0..60ca6e1 100644 --- a/rtl/src/rom.v +++ b/rtl/src/rom.v @@ -2,27 +2,27 @@ // Contains instructions of program. module rom #( - parameter N = 32, - parameter SIZE = 1024, - parameter ROM_FILE = "../../build/rom.hex" + parameter SIZE = 1024, + parameter ROM_FILE = "../../build/rom.hex" )( - input clk, - input [N-1:0] addr, - output reg [N-1:0] data_read + input clk, + input [31:0] addr, + output reg [31:0] rd ); -`include "include/log2.vh" +`include "include/consts.vh" + //(* RAM_STYLE="BLOCK" *) -reg [N-1:0] mem [0:SIZE-1]; +reg [31:0] mem [0:SIZE-1]; initial begin $readmemh(ROM_FILE, mem, 0, SIZE-1); end -always @(negedge clk) begin - data_read <= mem[addr >> 2]; +always @ (negedge clk) begin + rd <= mem[addr >> 2]; end endmodule |