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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-23 08:20:16 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-23 08:20:16 +0200
commit6a9573628b3c7e537bd273a483be9abcfa2ee429 (patch)
treeacc804258af80527e3f606b709cb2fe8e36593a9 /rtl/src/rom.v
parentc6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 (diff)
downloadriscv_cpu-6a9573628b3c7e537bd273a483be9abcfa2ee429.tar.gz
riscv_cpu-6a9573628b3c7e537bd273a483be9abcfa2ee429.zip
mem size
Diffstat (limited to 'rtl/src/rom.v')
-rw-r--r--rtl/src/rom.v17
1 files changed, 16 insertions, 1 deletions
diff --git a/rtl/src/rom.v b/rtl/src/rom.v
index 60ca6e1..6cb9a92 100644
--- a/rtl/src/rom.v
+++ b/rtl/src/rom.v
@@ -7,6 +7,7 @@ module rom #(
)(
input clk,
input [31:0] addr,
+ input [2:0] size,
output reg [31:0] rd
);
@@ -21,8 +22,22 @@ initial begin
$readmemh(ROM_FILE, mem, 0, SIZE-1);
end
+wire [31:0] rd_w;
+wire [15:0] rd_h;
+wire [7:0] rd_b;
+assign rd_w = mem[addr >> 2];
+assign rd_h = (mem[addr >> 2] >> (addr[1] * 16)) & 32'hFFFF;
+assign rd_b = (mem[addr >> 2] >> (addr[1:0] * 8)) & 32'hFF;
+
always @ (negedge clk) begin
- rd <= mem[addr >> 2];
+ case (size)
+ FUNCT3_LS_W: rd <= rd_w;
+ FUNCT3_LS_H: rd <= { {16{rd_h[15]}}, rd_h };
+ FUNCT3_LS_B: rd <= { {24{rd_b[7]}}, rd_b };
+ FUNCT3_LS_HU: rd <= rd_b;
+ FUNCT3_LS_BU: rd <= rd_h;
+ default: rd <= rd_w;
+ endcase
end
endmodule