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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-06-28 16:10:11 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-06-28 16:10:11 +0200
commit04a934987445897a03652aa73e2a5c5088d40ba1 (patch)
treeeb9ecb1cf1a68ef5fa602d0581b8046b39fe8406 /rtl/src/rom.v
parent94954f13818a55aae02b660942abd12dab32372d (diff)
downloadriscv_cpu-04a934987445897a03652aa73e2a5c5088d40ba1.tar.gz
riscv_cpu-04a934987445897a03652aa73e2a5c5088d40ba1.zip
added ddca notes referenceHEADmaster
Diffstat (limited to 'rtl/src/rom.v')
-rw-r--r--rtl/src/rom.v2
1 files changed, 0 insertions, 2 deletions
diff --git a/rtl/src/rom.v b/rtl/src/rom.v
index 9ade9bc..784e50d 100644
--- a/rtl/src/rom.v
+++ b/rtl/src/rom.v
@@ -18,8 +18,6 @@ module rom #(
//(* RAM_STYLE="BLOCK" *)
reg [31:0] mem [0:SIZE-1];
-reg [7:0] mem0, mem1, mem2, mem3;
-
reg [31:0] rd_reg;
reg [31:0] addr_reg;