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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 13:50:28 +0200 |
| commit | cb0be9e2039569ee7d18657e8f675d1f8369b407 (patch) | |
| tree | 91fa71b3960d1ad5217759371143efbdd833d475 /rtl/src/reset_synchronizer.v | |
| parent | 98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff) | |
| download | riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip | |
restructured project
Diffstat (limited to 'rtl/src/reset_synchronizer.v')
| -rw-r--r-- | rtl/src/reset_synchronizer.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/rtl/src/reset_synchronizer.v b/rtl/src/reset_synchronizer.v new file mode 100644 index 0000000..dc7a80a --- /dev/null +++ b/rtl/src/reset_synchronizer.v @@ -0,0 +1,16 @@ +module reset_synchronizer ( + input clk, + input rstn_async, + output rstn +); + +reg [1:0] rstn_sync; + +always @(posedge clk or negedge rstn_async) begin + if (!rstn_async) rstn_sync <= 2'b00; + else rstn_sync <= {rstn_sync[0], 1'b1}; +end + +assign rstn = rstn_sync[1]; + +endmodule
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